Statistical delta modulation system



6 Sheets-Sheet 1 LOW DECODER INTEGRATOR 26 "22 *2 IIIIIIIIIIIIIIIIIIIIT. L. FINE STATISTICAL DELTA MODULATION SYSTEM PRIOR ART Ia Is "I? I9 2I23 25 "2 I2 *I4 Is Is l I I I I CLOCK PULSE GENERATOR PULSE MODULATORENCODER 3 *5 *7 *9 'II o '2' "4 6 "8| Io COMPARATOR July 16, 1968 FiledOct. 25, 1965 5" INTEGRATOR il I I I I I I I I I I I I I I I I IINVENTOR.

I1 04/4, ATTORNEYS I IIIII D E E S E H T N Y S o 2 4 6 a I0 "I 9 T. L.FINE July 16, 1968 STATISTICAL DELTA MODULATION SYSTEM 6 Sheets-Sheet 3Filed Oct. 23, 1965 ZOCDDmPwZOOMm ombjsooiwo 255w 20 525 BEzwz E r N. m.v a m. t S H ILO MON

INVENTOR. TERRENCE L. FINE ATTORNEYS T L. FINE July 16, 1968 STATISTICALDELTA MODULATION SYSTEM 6 Sheets-Sheet 5 Filed Oct. 25, 1965 AT DECODERINHIBIT SHIFT PULSES SYNCH. SIGNALS SHIFT y- PULSE GEN.

34 THIRD STAGE A S OND 8 GE 32 FIRST STAGE INVENTOR. TERRENCE L. FINE FIG. 7

ATTORNEYS BY W gL July 16, 1968 T. L. FINE STATISTICAL DELTA MODULATIONSYSTEM Filed Oct. 25, 1965 6 Sheets-Sheet 6 |II|.|| I III I I. ll.llllllllllll [IJ m 9 n Q Q J u a Q n 10:26 5:26 5:3 I856 u s mm mm m omr lllllllllllllllllllllllllllll |l| J mv zmo hmz 292223 m 5 u 3 Fill 1|IIIL ll @9538: k w Eda wm sm 9 w r Q INVENTOR. TERRENCE L. FINE BY W 4/M ATTORNEYS United States Patent 3,393,364 STATISTICAL DELTA MODULATIONSYSTEM Terrence L. Fine, Berkeley, Calif., assignor to Signatron, Inc.,Lexington, Mass., a corporation of Massachusetts Filed Oct. 23, 1965,Ser. No. 502,911 14 Claims. (Cl. 325-38) This invention relates ingeneral to the transmission of analog data by digital signals. Moreparticularly, the invention concerns an improved delta modulation systemwhich minimizes the error between the actual value of the analog signalat the transmitter and the value that is decoded at the receiver.

A delta modulation system is a type of pulse communication system inwhich an analog signal is intermittently sampled and, instead of theabsolute signal amplitude being transmitted at each sampling, only thechange occurring in the analog signal from one sample to the next isconveyed by the transmitted pulses. In the conventional delta modulationsystem, the direction of change is indicated at each sampling and notthe magnitude of the change. Because the conventional delta modulationsystem is limited to a unit amplitude level change per pulse, theconventional system is seriously deficient in its ability to follow asignal whose change in amplitude from one sampling instant to the nextexceeds the unit level of the system. That is, the conventional deltamodulation system has a maximum rate of change of amplitude which theinput signal ought not to exceed. Where the input signal does exceedthat maximum rate of amplitude change, the conventional systemintroduces a large error so that the signal reconstructed at the decoderof the system is not a faithful replica of the input signal.

The present invention substantially reduces the deficiencies of theconventional delta modulation system.

The invention resides in a statistical delta modulation systemutilizing, in its encoder, a comparator which intermittently comparesthe input analog signal with a level setting supplied from a store of 2level values. The level setting used in the comparator is determined bythe sequence of delta modulated pulses resulting from a number of theimmediately preceding comparisons, where that number is represented bythe memory length m. The 2 level values are, where feasible, determinedanalytically from the statistical properties of the input analog signal.In effect, the statistical delta modulation system employs the mostrecent segment of the past history of comparisons with the input analogsignal to determine, on a statistical basis, the level setting that willmost closely approximate the actual level of the analog signal at thenext comparison. That is, the sequence of delta modulated pulsesproduced during an immediately preceding interval m, is employed toselect the level setting to be used in the next comparison. The decoderemployed in the statistical delta modulation system utilizes a set of 2reconstruction level values to regenerate the input signal waveform. Thesequence of the last k received signals is utilized to select thereconstruction level value used in the regeneration. The 2reconstruction level values are, preferably, determined analyticallyfrom the statistical properties of the input analog signal.

The invention, both as to its arrangement and its manner of operation,can be more readily apprehended from the exposition which follows whenconsidered in conjunction With the accompanying drawings in which:

FIG. 1 illustrates the scheme of a conventional delta modulation system;

FIG. 2A shows waveforms employed in the discussion of the conventionaldelta modulation system;

FIG. 2B depicts the delta modulated pulse signals associated with FIG.2A;

3,393,364 Patented July 16, 1968 FIG. 2C is a timing diagram used inconnection with FIGS. 2A and 23;

FIG. 3 illustrates the slope limited action of the conventional deltamodulation system;

FIG. 4 depicts the scheme of a system embodying the invention;

FIGS. 5A, 5B, 5C, and 5D are diagrams pertaining to the operation of thestatistical delta modulation system depicted in FIG. 4;

FIG. 6 shows details of the apparatus employed in the encoder of theinvention;

FIG. 7 shows details of the apparatus employed in the decoder of theinvention; and

FIG. 8 depicts apparatus that may be employed in the encoder of theinvention in lieu of the structural arrangement illustrated in FIG. 6.

FIG. 1 depicts the scheme of a conventional delta modulation systemhaving an encoder 1 at the transmitter and a decoder 2 at the receiver.For expository purposes, it is assumed that the intelligence or messageto be transmitted is the waveform c of FIG. 2A. At the transmitter, thewaveform s is encoded as a train of pulses and at the received thepulses are utilized to reconstruct the original waveform.

The encoder portion of the conventional delta modulation system employsa clock pulse generator 3 which periodically emits a pulse to modulator4. The modulator emits a positive or negative pulse for each clock pulsefrom generator 3. The output of the modulator is impressed upon anintegrating network 5 which has its output coupled to an input ofcomparator 6. The comparator is a device which compares the amplitude ofthe integrated signal :2 with the signal :2 which is applied to theother input of the comparator and provides an output signal e whosepolarity is determined by the sense of the difference. That is, wherethe amplitude of the integrated signal e is larger than the amplitude ofsignal e at time t the output signal e(t from the comparator is, forexample, a positive signal, whereas if the integrated signal e issmaller than the amplitude of signal e at time t the output signal e(lis a negative signal. The output 15 of the comparator governs pulsemodulator 4 and causes the modulator to emit a positive pulse where thedifference signal 6(Z) is of one electrical polarity or emit a negativepulse where the difference signal e(t) is of the other electricalpolarity. The comparator, therefore, determines at each sampling instantt whether the pulse emitted by the modulator is a positive pulse or anegative pulse and the decision depends upon the amplitude of thefeedback signal 2 obtained from the integrator at time t. Sampling ofthe input signal is done at periodic intervals t t t t which aredetermined by the clock pulses from pulse generator 3.

The train of clock pulses supplied by pulse generator 3 is shown in'FIG. 2C, the train of positive and negative pulses emitted by modulator4 is depicted in FIG. 2B, and the integrated signal e supplied tocomparator 6 is shown in FIG. 2A. The delta modulated pulse output ofmodulator 4 is applied to integrator 5 and results in the waveform e Foreach positive pulse in the delta modulated train e waveform e rises byone unit step and for each negative pulse in the delta modulated train ethe waveform e falls by one unit step. Signal 2 therefore, is a steppedwaveform which can change only by one unit step from one samplinginterval to the next. In comparator 6, waveform 2 is compared with inputsignal s The output of the comparator at sampling time 1 determines whatthe polarity of the output pulse from modulator 4 should be to correctfor the difference between the amplitudes of the compared signals. Thefeedback system in the encoder acts to reduce the dilference by causingthe synthesized signal 2 to step up or down to follow the message signale :In effect, the change in signal amplitude from one sampling instantto the next is transmit-ted in a delta modulation system rather than theabsolute signal amplitude at each sampling instant.

In practice, the negative pulses in the delta modulated train 2 may beomitted in the transmission of the coded signals without affecting thelogical design of the receiver.

At the receiver, the delta modulated pulse train e is impressed upon thedecoder portion of the system. The decoder utilizes an integratingnetwork 7 whose output is coupled to a low pass filter 8. In thedecoder, the delta modulated pulse train e is again integrated to resultin the stepped voltage waveform e, which consists of the originalmessage Waveform 2 plus noise components due to quantization andsampling. By passing the 2 signal through low pass filter 8, thequantization and sampling noise components are substantially removed sothat the reconstructed signal e at the filters output is a close replicaof message signal e In the conventional delta modulation system, theinformation contained in the transmitted pulses is correlated to changesof the input signal and not to the absolute amplitude of the signal.That is, the transmitted pulses indicate the direction of change in theinput signal at each sampling but do not indicate the magnitude of thechange. Because the synthesized wave can change only one level per clockpulse, the synthesized wave cannot closely follow the analog waveformwhere the analog signal has a large and abrupt change in amplitude. Thelargest slope the conventional system can reproduce is one changing byone level or step every pulse interval. For example, in FIG. 3, thesynthesized wave is shown increasing by one level from t to t That is,the synthesized wave required ten pulse intervals to achieve its peak topeak amplitude. If the analog signal rises from peak to peak in fivepulse intervals, the synthesized wave cannot closely follow that rise.Thus the slope of the synthesized wave in the conventional deltamodulation system is limited to one step for every pulse interval.

The invention resides in the improved delta, modulation systemschematically depicted in FIG. 4. That system is intended to be tailoredto the statistical properties of the input analog data which is to betransmitted. If the statistical properties of the input analog data areknown, the optimum design of the system can be determined analytically.Where the statistical properties of the input data are not known, but asample of the input data is available, the optimum design may beestimated.

The design of the encoder in the statistical delta modulation systemdepends on the number of past samples which are taken of the analoginput signal and employed in the generation of each output from thepulse modulator. The number of samples employed in the generation ofeach output from the modulator is denoted by m, which is called thememory length. In the system of FIG. 4, the encoder 111* employs a pulsegenerator 11 to intermittently supply a pulse to pulse modulator 12. Forthe purpose of this discussion, it is assumed that the pulses fromgenerator 11 are emitted periodically, although in the general case thepulses need only be emitted intermittently. The pulse modulator emits apositive or negative pulse for each clock pulse from generator 11. Forpurposes of this exposition, a positive pulse has a binary value of +1and a negative pulse has a binary value of -1. The determination ofwhether pulse modulator 12 emits a +1 digit signal or a 1 digit signalis controlled by a signal a coupled to the modulator from a comparator13. The analog signal I(t) is applied as one input to comparator '13 andthe other input L is a level setting voltage supplied from a set ofvoltage level values available from store 14. In the comparator theinput analog signal I'(t) is compared with the level setting L and thecomparator emits a signal 6 indicating the sense of the differencebetween the compared signals. That is where the level setting L islarger than the amplitude of Hz) at time t the output signal 4 e(t fromthe comparator is, for example, a positive signal, whereas if the levelsetting L is smaller than the amplitude of :I'(t) at time t the outputsignal e(t is a negative signal. In effect, the input analog signal I(t)is sampled once for each clock pulse emitted by clock pulse generator 11and the sample is compared against the level setting L The sampled valueof I(t) at time t is here denoted by I IHZIUR) The sampled values I Ioccurring respectively at times t t result in the emission of signalse(t e(t from comparator 13 which cause pulse modulator to emit binarydigital signals S S each signal having a binary value that is either 1or +1. The nth binary digital sign-a1 emitted by the pulse modulator isdenoted 5,, where S is either +1 or +1.

In the encoder portion of the statistical delta modulation system, theessence of the invention resides in the selection of the level setting LIn the conventional delta modulation system depicted in FIG. 1, thelevel setting signal is the (2 signal obtained from the integrator 5which integrates the positive pulses (+1s) and the negative pulses (-ls)emitted by modulator 4. In the encoder 10 of the statistical deltamodulation system, the level setting signal L is one of 2 level valuesselected from the set of level values held in store 14. The 2*" storedlevel values, l 1 are determined analytically if the statisticalproperties of the input analog signal are known. Otherwise, the levelvalues can be estimated from available data. The level setting L chosenfrom the stored set, is determined by a level value selector 15 to bethe best choice for the particular sequence of previously generated mbinary digits held in a binary signal storage device 16.

Assuming, .for example, that the statistical delta modulation system ofFIG. 4 has a memory length m =2 and that two digital signals S and Spreviously emitted by modulator 12 are entered in binary store 16, thenupon the occurrence of the next clock pulse at time I the analog sample1 is to be compared to a level setting L Because each of the twopreviously generated binary digital signals S and S may have a digitalvalue of +1 or 1, there are 2 =4 possible sequences of those binarydigits, thus For each sequence, there corresponds a pro-computed levelvalue l l l or Therefore, four (i.e. 2 level values have beenpre-computed and are available from store 14. The particular sequence SS entered in binary store 16 causes level value selector 15 to choosethe proper level value from the set in store 14 and that chosen levelvalue becomes level setting L with which I is compared in comparator 13.Where the voltage amplitude, of I exceeds level setting L the e(t signalfrom the comparator causes pulse modulator 12 to emit a positive pulse,denoting that S =+l; where the amplitude of I is less than level settingL the E(t3) signal from the comparator causes the pulse modulator toemit a negative pulse, denoting that S =1.

At the start of the transmission, binary store 16 may initially befilled with arbitrarily chosen digits. The improper transient whichresults from having initially inserted arbitrarily chosen digits inbinary store 16 gradually dies out as the transmission progresses, withthe result that the system pulls in to proper operation. The pull intime can be shortened by using 2 -1 additional level values I I l (2 1).Level value Z in store 14, is used to generate S after the first analogvoltage sample I is taken in comparator 13. At the time that level value1 is used there are as yet no signals in store 16. After S enters store16, one of two additional level values I and 1 in store 14, can bechosen by selector to be applied to comparator 13 for comparison withanalog sample I Level value I is selected Where the binary value of S is1, whereas level value I is chosen where the binary value of S is +1.The comparison of I with either level setting 1 or level setting Iresults in the generation of S by modulator 12. After S and S areentered in binary store 16, selector 15 chooses one of the four levelvalues l or and the operation is as described previously. After thegeneration of S and S the start-up level values 1 I and are not neededunless transmission is interrupted and must be commenced again.

Where the encoder is intended to have rapid pull in, there are in thisexample a total of seven level values constituting the set in store 14,three of the levels being used in the start-up phase of the transmissionand the other four levels being used after the start-up phase. In atypical statistical delta modulation system we may, by way of example,adopt the following rules for choosing the level setting L andthereafter the level setting L is chosen as follows:

The decoder 18 of the statistical delta modulation system of FIG. 4employs a binary storage device 19 in which are stored the last m+ldigits corresponding to the transmitted binary signals S S The signals SS received at the decoder may differ, in a practical situation, from thetransmitted signals because in travelling through the communicationschannel 17, some of the information may be transposed or may be lost dueto noise in the channel. The purpose of the decoder is to regenerate theoriginal signal samples; that is, the decoder operates to reconstructthe sampled values I of the ana log waveform. By employing a smoothingfilter 22, the reconstructed samples may be utilized to obtain a replicaof the original analog signal Waveform. The decoder has 2 possiblereconstruction values r r r2m+1 available from store 21. There is acomputational advantage for the system if the memory lengths of theencoder and decoder are respectively an and m+1. It is possible,however, for the encoder and decoder to have other memory lengths. Eachof the reconstruction values r r r2m+1 is pre-computed in advance tocorrespond to one of the 2 possible sequences of the m'+1 binary digitsentered in store 19. That storage device enters and stores the last m+1binary digital signals, including the currently received digital signalS When the initial m binary digits are entered in store 19,reconstruction level value selector chooses from store 21 areconstruction of I called R for every new digital signal 8,, thereafterentered. Preferably the reconstruction values are applied to the inputof a smoothing filter 21 Whose characteristies are statisticallydesigned so that it yields a faithful replica of the encoders inputanalog waveform.

To illustrate the operation of the statistical delta modulation systemof FIG. 4 when the channel is noiseless, the input analog signal appliedto comparator 13 is depicted in FIG. 5A as waveform I(t). At times t t tthat waveform is compared in comparator 13 with level settings obtainedfrom store 14. A possible set of level values 1 I I l l l and I isindicated in FIG. 5A. At time t the analog waveform is compared withlevel setting I and, because the level setting is below the amplitude ofthe analog waveform, pulse modulator 12 emits a +1 binary signal andthat signal, S is also transmitted, as indicated in FIG. SC, to thedecoder. Signal S is also entered into binary store 16 and causesselector 15 to choose level as the level setting L that is applied tocomparator 13. At time t therefore, the analog waveform is compared incomparator 13 with level setting I 3, causing the next signal S emittedby modulator 12 to be a +1 binary digital signal. Upon the entry of Sinto store 16, the sequence of S and S causes selector 15 to chooselevel value L; from store 14 and that value then becomes the levelsetting in comparator 13. At time t;,, the analog signal is comparedwith level setting and because the analog signal is above that level,pulse modulator 12 emits S as a +1 signal. Upon being entered intobinary store 16, the sequence of S and S cause selector 15 to againselect level value from store 14. The next comparison, at time t incomparator 13 is therefore made with the level setting. By a repetitionof the described process, the sequence of level settings in comparator13 which ensues is indicated in FIG. 5B.

At the decoder, the binary data stream of FIG. 5C is received and theinitial m+l digits are entered into binary store 19. Based upon thesequence of digital signals, S S S in the binary store, selector 20chooses the reconstruction R in accordance with the following rules:

The first three signals S S S in the transmitted binary data stream areall +1s; hence, the sequence of binary digits initially entered intostore 18 in the decoder is +1, +1, +1. In accordance with the foregoingrules, selector 20 causes the largest reconstruction value r to beemitted from store 21, as indicated in the reconstructed waveformdepicted in FIG. 5D. Because S S S and S are all +1s, the selectorcontinues to select the r reconstruction value four more times. Showever, is a 1 and therefore the sequence, when that signal is enteredin store 19, becomes +1, +1, 1, which corresponds to reconstructionvalue r Therefore, selector 20 causes store 21 to emit reconstructionvalue r when S enters binary store 19. S is also a 1, so that upon itsentry into store 19, the sequence becomes +1, -1, 1, which correspondsto reconstruction value Selector 20, therefore, causes store 21 to emitreconstruction value r when S enters binary store 19. S is a 1 digit andwhen that signal enters store 19, the sequence becomes l, 1, -1.Selector 20, upon the entry of S into store 19, causes reconstructionvalue r to be emitted from store 21. The peak to peak change from r to rcan therefore be brought about by three successive signals. This exampleillustrates the capability of the statistical delta modulation system torespond much faster than the conventional delta modulation system tochanges in the analog input signal and to thereby minimize the slopelimiting encountered in the conventional system.

The techniques employed in determining the numerical values of the levelvalues in the encoder and the reconstruction values in the decoder areset forth below. The equations here employed are based on a noiselesschannel and on a minimum mean square error criterion; that is onminimizing (I R The equations are used here only as examples as thedesign can be effected for other criteria and for noisy channels. For ageneral discussion regarding optimum design of a delta modulationsystem, see Properties of an Optimum Digital System and Applications byTerrence Fine, appearing in the IEEE Transactions on 7 InformationTheory, vol. IT1(), No. 4, October 1964, at pages 287 to 296. Thenotation herein employed is .S:=sequence of the last m transmittedsignals beginning with S i.e., S S S S S +=the set of transmittedsignals defined by:

n n-l S =the set of transmitted signals defined by:

The equations for the level values and reconstruction values becomeuncoupled if Equation (2) is substituted into Equation (1). Uponsubstituting there is obtained:

It should be observed that L is determined before S is transmitted,while R is determined after S is received. Thus, Equation (3) shows thatthe level setting should be the arithmetic average of the two expectedvalues of the input signal given that the past transmission formed thesequence S and S =+1 or S =1. Those expectations can be foundanalytically if the m+1 order joint probability density function of theinput process I(t) is known. The two reconstruction values correspondingto the same past transmitted sequences S but differing present receivedsignals S are determined in the process of finding the level values.

In practice, the m+1 order probability density function of theinformation source may not be known, but representative input data maybe available. In that case, the evaluation of the level values andreconstruction values need not be performed by first determiningprobability densities but can instead be found directly throughestimation of the proper design parameters. To perform this estimation,it is necessary to have a sufficiently long input record that can bedivided into many 2 independent segments of m samples. A schemeanalogous to Equation (3) can be programmed on a computer whereby thelevel value is automatically sought until it coincides with thearithmetic mean of the averages of the samples above and below the levelvalue. The output reconstruction value R for a given sequence could thenbe estimated by the average of the sample values I which fall above orbelow the level setting L found for a particular transmitted sequence SA start-up phase must again be considered as in the case of theanalytical technique. For a system of memory length min the encoder andm+1 in the receiver, there are again twice as many output reconstructionvalues as there are level setting values employed after the start-upphase.

It is of utmost importance to note that the analysis represented byEquations (2) and (3) is required only in the synthesis phase of astatistical delta modulation system design. Once the actual numericalvalues of the level values and the reconstruction values have beendetermined, these values are placed in a store and are selected inaccordance with the sequence of the last in digits in the encoder andthe last m+1 digits in the decoder.

Referring again to the encoder depicted in FIG. 4, the binary store 16may be simply a shift register having m flip-flop stages. In FIG. 6, thebinary store is illustrated as a shift register having two (m=2)flip-flop stages 23 and 24. The modulator 12 has two outputs, one outputproviding the +1 pulse signals and the other output providing the :1output signals. As the negative pulses in the delta modulated train are,in practice, omitted in the transmission of the coded signals, only thepositive pulse output of the modulator is coupled into the transmissionchannel. Upon the emission of a pulse from modulator 12, the informationin flip-flop 24 is shifted out of the register, the information inflip-flop 23 is shifted to flipflop 24, and the pulse itself is enteredinto flip-flop 23. That is, upon the emission of a pulse from modulator12, information is shifted through the register 16. As no third stagefollows flip-flop 24, the information shifted out of that flip-flop islost. The register 16 may be of the self-shifting type or clock pulsegenerator 11 may be used as a source of shift pulses for the register.

Shift register 16 provides four output signals, two outputs beingobtained from flip-flop 23 and the other two outputs being obtained fromflip-flop 24. One output of each flip-flop is marked with +1 to indicatethat that output is at ground potential when a +1 signal is stored inthe flip-flop. The other output of the flip-flop is marked 1 to indicatethat that output is at ground potential when a -1 signal is stored inthe flip-flop. Each flip-flop is constructed so that when one output isat ground potential, the other output is at a positive voltage. Hence,if a 1 signal is stored in flip-flop 24, its 1 output is at groundpotential and its +1 output emits a positive voltage. Each of the fouroutputs of the shift register 16 is connected to a switching matrixwhich constitutes level value selector 15. Because of the arrangement ofdiodes in the switching matrix, the topmost horizontal line 25 of thematrix is at ground potential only when the sequence of digital signalsin the shift register 16 is -1, 1. Horizontal line 26 is at groundpotential only when the sequence of digital signals in the shiftregister is +1, 1; horizontal line 27 is at ground potential only whenthe sequence of digital signals is -1, +1; and horizontal line 28 is atground potential only when the sequence of digital signals is +1, +1.Each of the horizontal lines of the switching matrix is coupled to a NORgate in store 14. Each NOR gate 29, 30, 31, and 32 is constructed sothat when its input is at a positive potential, it provides no outputsignal and when its input is at ground potential, it provides a signalat a specified voltage. The input to NOR gate 29 is obtained from line25 of the switching matrix and when that input is at ground potential,NOR gate 29 emits a signal at level value 1 The input to NOR gate 30 isobtained from line 26 of the switching matrix and when that input is atground potential, NOR gate 30 emits a signal at level value Similarly,NOR gate 31 emits a signal at level value 1 when line 27 is at groundpotential and NOR gate 32 emits an level value signal when line 28 is atground potential. Because of the switching matrix, only one NOR gate canemit a signal at any one time, and the level value of that signal isdetermined by the sequence of digits in shift register 16. The levelvalue signal constitutes the level setting L that is applied tocomparator 13 in FIG. 4.

In the decoder 18 (FIG. 4), the binary store 19 may, as indicated inFIG. 7, be a shift register having three (m+1=3) flip-flop stages 32,33, and 34. Where the negative pulses have been removed in transmissionof the delta modulated pulse train, a shift pulse generator 35 isemployed to shift information along register 19. The shift pulsegenerator is synchronized by the pulses in the received train.Reconstruction level value selector 20 is a switching matrix similar tothat employed in the encoder. The set of 2 reconstruction level valuesin store 21 is furnished by NOR gates 36, 37, 38, 39, 40, 41, 42, and43. Each horizontal line in switching matrix 20 provides the input to adifferent one of the NOR gates. Each vertical line in the switchingmatrix is coupled to an output of a flip-flop in shift register 19. Theoutputs of flip-flops 32, 33, and 34 are marked +1 and -1 to indicatewhen those outputs are at ground potential, as previously explained inconnection with the flip-flops in register 16. When the sequence ofdigits shown at the left of the horizontal lines in the switching matrixare entered in shift register 19, NOR gate 36 emits a signal at levelvalue r NOR gate 37 emits a signal at level value r NOR gate 38 emits asignal at level value r and so forth for NOR gates 39 to 43. Because ofthe diode arrangement in switching matrix 20, only one NOR gate can emita signal at any one time and the level value of that signal isdetermined by the sequence of binary digits in shift register 19. Thereconstruction level value signals emitted by the NOR gates may becoupled to the input of smoothing filter 22 so as to obtain a waveformmore nearly approaching the form of the input analog signal. To preventtransients, arising from the shifting of information in register 19,from interfering with the operation of the decoder, the shift pulsesfrom generator 35 may be employed to prevent all the NOR gates fromfurnishing any output signals during the time that information isshifted in the register.

In lieu of using an encoder having a shift register as the binary store16 and a switching matrix as the selector 15, as shown in FIG. 6, theapparatus schematically shown in FIG. 8 may be employed. The positiveand negative pulses from modulator 12 are applied to serially connectedpulse delay networks 45, 46. Because of the delay networks, when pulse Sis at the output of delay network 46, the succeeding pulse S is at theoutput of delay network 45. The output of delay network 45 is coupled tothe input of an amplifier 47 and the output of delay network 46 iscoupled to the input of an amplifier 48. Preferably, the gain ofamplifier 47 is unity (viz, G=2) and amplifier 48 has a gain of 2 (viz,G=2 The choice of amplifier gain is not critical, as long as the gain ofamplifier 48 is twice larger than the gain of amplifier 47. The outputsof amplifiers 47 and 48 are coupled to a summation network 49 which addsthe outputs from the two amplifiers and emits a signal indicating thetotal of the inputs. The output signal of the summation network isapplied to a set of four switches, 50, 51, 52, and 53, each switch whenclosed, emitting a signal at one of the level values, l l l or 1 Theamplitude of the voltage emitted by summation network is governed by thesequence of the S and S signals. When the signal from pulse modulator 12has a binary value of +1, a positive pulse appears on line 54, whereaswhen the signal from pulse modulator 12 is a binary -l, a negative pulseappears on line 54. Therefore, where S and S,, are both 1s, the outputof summation network may for example be 3 volts, causing switch 50 toclose and apply level value to comparator 13. Where the sequence of S,,and S,, is +1, 1, the output of summation network may for example be 1volt, causing switch 51 to close and apply level value l; to thecomparator. Where the sequence of S,, and S,, is 1, +1, the output ofsummation network may for example be +1 volt, causing switch 52 to closeand apply level value to the comparator. Where the sequence of S and Sis +1, +1, the output of summation network may for example be +3 volts,whereby switch 53 is caused to close and apply level value 1 tocomparator 13. Switches 50, 51, 52, and 53 are therefore responsive tothe magnitude of the output from summation network 49, and the switchesare arranged so that only one switch at a time can be closed.

In the arrangement illustrated in FIG. 8, the binary store 16 for thelast m digits is provided by delay networks 45 and 46; the level valueselector is constituted by the signal amplifiers 47, 48 which, ineffect, give binary weight to the S,, and S,, signals according to theirposition in the sequence of in digits, and by the summation network 49which totals the weighted signals; and the store 14 for the set of 2level values is provided by switches 50, 51, 52, and 53.

In the embodiments depicted in FIGS. 6, 7, and 8, the logical NOR gatesand the switches 50 to 53 which produce the level setting values wereassumed to provide analog signals. The level value signals, however,need not be analog signals, but rather may be digital signals. In FIG.4, for example, the level setting L may be a digital signal which iscompared, not directly with the analog signal, but with a digitizedequivalent of the analog signal. Thus, comparator 13, rather thancomparing analog signals, may compare digital signals. The basic schemeof the invention remains unaltered regardless of whether the comparedsignals take the form of analog signals or of digital signals.

The invention has been described as embodied in a binary system.However, the invention may be utilized in an n-ary system; that is, theinvention may be used in a digital system having n permissible values. Abinary system is merely an n-ary system where n=2. In an Wary systemwhere n exceeds two (n 2), the comparator takes the form of an n-levelquantizer. In essence, the comparator compares the I signal with aplurality of windows, each window including all amplitude values betweensuccessive thresholds. The threshold values which determine the windowsare selected from the store of n sets of level values in accordance withan address determined by the sequence of digits in n-ary store 16. Thecomparator quantizes the I by sequential comparison with the windows.Alternatively, the comparator may comprise -a plurality of stages whichsimultaneously compare the I with every window in the set, and the stagehaving the window in which the I, is contained emits a signal to thepuls generator 12 causing it to generate the proper one of the n-arysignals.

In view of the multitude of ways in which the invention can be embodied,it is not intended that the scope of the invention be restricted to theprecise structure illustrated in the drawings or described in thespecification. Rather it is intended that the scope of the invention belimited by the claims appended hereto and to include such structures asdo not in essence fairly depart fmm the invention there defined.

What is claimed is:

1. A delta modulation system comprising:

(A) an encoder having 1) a store of 2 level values,

(2) a comparator for intermittently comparing an input analog signalwith a level setting supplied from the store of 2 level values,

(3) means for emitting a binary digital signal whose binary value isdetermined by the comparison made in the comparator,

(4) a storage device for storing in sequence in of the last digitalsignals emitted by said means,

(5) and a level value selector controlled by the sequence of digitalsignals in the storage device, the level value selector causing thelevel setting supplied to the comparator to be selected from the storeof 2 level values;

(B) and a decoder having (1) a store containing a set of 2reconstruction level values,

(2) a storage device for storing in sequence k of the last receiveddigital signals,

(3) and a reconstruction level value selector controlled by the sequenceof digital signals in the storage device, the selector causing areconstruction level value signal to be emitted from the storecontaining the set of reconstruction level values.

2. A delta modulation system encoder comprising:

a store of 2 level setting values;

a comparator for periodically comparing an input analog signal with alevel setting signal supplied from the store of 2 level setting values;

wherein the storage device for storing the last in digital signals is ashift register having a bistable stage for each digital signal of the mdigital signals.

4. A delta modulation system encoder as in claim 3,

wherein the level value selector is a switching matrix controlled by thesequence of digital signals in the binary storage device.

5. A delta modulation system encoder in claim d, wherethe store of 2level setting values is provided by a set of logical gates, each logicalgate obtaining its input signal from the switching matrix, and eachlogical gate providing a different one of the 2 level setting values.

6. A delta modulation system encoder comprising:

a plurality of signal controlled switches providing a store of 2 levelsetting values, each switch responding to an input signal of a difierentmagnitude by providing one of the 2 level setting values;

a comparator for intermittently comparing an input analog signal with alevel setting signal provided by one of the signal controlled switches;

a pulse modulator for emitting a binary digital signal whose binaryvalue is determined by the comparison made in the comparator;

a storage device for storing the last m digital signals emitted by thepulse modulator;

and means controlled by the sequence of the last m digital signals inthe storage device for applying to the signal controlled switches asignal whose magnitude is different for each sequence of the last mdigital signals.

7. A delta modulation system encoder comprising:

a plurality of voltage controlled switches, each switch providing adifierent one of 2 level setting values;

a comparator for intermittently comparing an input analog signal with alevel setting signal provided by one of the voltage controlled switches;

a pulse modulator for emitting a binary digital signal whose binaryvalue is determined by the comparison made in the comparator;

signal delay apparatus coupled to the output of the pulse modulationwhereby the least in digital signals emitted by the pulse modulatorexist concurrently in the apparatus;

and means controlled by the sequence of the last m digital signals inthe delay apparatus for applying to the voltage controlled switches avoltage whose magnitude is different for each possible sequence of thelast in digital signals.

8. A delta modulation system encoder comprising:

a plurality of voltage controlled switches, each switch providing adifferent one of 2 level setting values;

a comparator for intermittently comparing an input analog signal with alevel setting signal provided by one of the voltage controlled switches;

a pulse modulator for emitting a binary digital signal whose binaryvalue is determined by the comparison made in the comparator;

signal delay apparatus coupled to the output of the pulse modulationwhereby the last m digital signals emitted by the pulse modulator existconcurrently in the apparatus;

means connected to the signal delay apparatus for converting the last mdigital signals to binary weighted signals; and

means for summing the binary weighted signals and applying the summationsignal to the voltage controlled switches.

9. A delta modulation system decoder, comprising:

a store containing a set of 2 reconstruction level values;

a storage device for storing in sequence the last k received digitalsignals;

and a reconstruction value selector controlled by the sequence of the kdigital signals in the storage device, the selector causing areconstruction level value signal to be emitted from the storecontaining the set of 2 reconstruction level values.

10. A delta modulation system decoder according to claim 9, wherein thestorage device for storing in sequence k of the last received digitalsignals is a shift register having a bistable stage for each of the ksignals.

11. A delta modulation system decoder according to claim 10, whereinclaim 11, wherein the store of 12 reconstruction level values isprovided by a set of logical gates, each logical gate having its inputcoupled to the switching matrix, and each logical gate providing adifferent one of the 2 level setting values.

13. A delta modulation system encoder comprising:

(1) a store of n level value sets, each set containing a plurality oflevels;

(2) a comparator for intermittently comparing an input signal with a setof the levels supplied from the store of n level value sets;

(3) means for emitting an n-ary signal whose n-ary value is determinedby the comparison made in the comparator;

(4) a storage device for storing in of the last n-ary signals emitted bysaid means;

(5 and a level value selector controlled by the sequence of n-arysignals in the storage device, the level value selector causing the setof level values supplied to the comparator to be selected from the storeof n level value sets.

14. A delta modulation system decoder comprising:

(1) a store containing a set of 11 reconstruction level values;

(2) a storage device for storing in sequence k of the last receiveddelta modulated signals;

(3) and a reconstruction level value selector controlled by the sequenceof signals in the storage device, the selector causing a reconstructionlevel value signal to be emitted from the store containing the set of nreconstruction level values.

References Cited UNITED STATES PATENTS 2,732,424 1/1956 Oliver179--15.55 X 2,905,756 9/ 1959 Graham 178-6 3,354,267 11/1967 Crater32538.1

ROBERT L. GRIFFIN, Primary Examiner.

J. T. STRATMAN, Assistant Examiner.

13. A DELTA MODULATION SYSTEM ENCODER COMPRISING: (1) A STORE OF NMLEVEL VALUE SETS, EACH SET CONTAINING A PLURALITY OF LEVELS; (2) ACOMPARATOR FOR INTERMITTENTLY COMPARING AN INPUT SIGNAL WITH A SET OFTHE LEVELS SUPPLIED FROM THE STORE OF NM LEVEL VALUE SETS; (3) MEANS FOREMITTING AN N-ARY SIGNAL WHOSE N-ARY VALUE IS DETERMINED BY THECOMPARISON MADE IN THE COMPARATOR; (4) A STORAGE DEVICE FOR STORING M OFTHE LAST N-ARY SIGNALS EMMITED BY SAID MEANS; (5) AND A LEVEL SELECTORCONTROLLED BY THE SEQUENCE OF N-ARY SIGNALS IN THE STORAGE DEVICE, THELEVEL VALUE